FIG. 6 is a perspective view illustrating a structure of a prior art field effect transistor (hereinafter referred to as an FET) including a heterojunction. In the figure, reference numeral 101 designates a semi-insulating GaAs substrate. A non-doped GaAs buffer layer 102 having a thickness larger than 1000 .ANG. is disposed on the semi-insulating GaAs substrate 101. An i(intrinsic)-type GaAs electron channel layer 103 having a thickness larger than 100 .ANG. is disposed on the non-doped GaAs buffer layer 102. An AlGaAs electron supply layer comprising Al.sub.0.25 Ga.sub.0.75 As containing Si as a donor impurity in a concentration of 1-3.times.10.sup.18 cm.sup.-3 and having a thickness of 350 to 450 .ANG. is disposed on the i-type GaAs electron channel layer 103. Reference numeral 105 designates a two dimensional electron gas formed at the heterojunction interface between the electron channel layer 103 and the electron supply layer 4. Reference numeral 110 designates an n-type GaAs contact layer containing Si in a concentration of 1-3.times.10.sup.18 cm.sup.-3 and having a thickness of 100 to 3000 .ANG.. A groove 109 is formed at the surface of the contact layer 110 reaching the electron supply layer 104, having a width of 100-3000 .ANG.. A source electrode 106 is disposed on the contact layer 110, a drain electrode 108 is disposed on the contact layer 110, and a gate electrode 107 is disposed in contact with the electron supply layer 104 at the recess groove 109.
FIGS. 7(a)-7(d) are cross sections of a production flow for producing the prior art field effect transistor. A buffer layer 102 and an i-GaAs electron supply layer 103 including no impurities are successively epitaxially grown on the semi-insulating GaAs substrate 101 as shown in FIG. 7(a). Then, an AlGaAs electron supply layer 104 containing dopant impurities and an n-GaAs contact layer 109 are epitaxially grown on the electron supply layer 103 as shown in FIG. 7(b). The contact layer 109 is etched to reach the electron supply layer 104 to form a groove 109 for forming a gate electrode as shown in FIG. 7(c) and, thereafter, a source electrode 106, a drain electrode 108, and a gate electrode 107 are respectively formed as shown in FIG. 7(d).
In the field effect transistor having a heterojunction of AlGaAs and GaAs, electrons generated from the donor impurities in the AlGaAs electron supply layer 104 move to the electron channel layer 103 comprising GaAs having a larger electron affinity than AlGaAs and are stored at the heterojunction interface between AlGaAs and GaAs. As a result, a two dimensional electron gas 105 comprising electrons stored in a two dimensional shape is formed in the GaAs electron channel layer 103. Since no dopant impurities are in the two dimensional electron gas 105, when a current flows between the source electrode 106 and the drain electrode 108, scattering due to the Si donor impurities is reduced to a great extent, providing a high electron mobility device.
In the prior art field effect transistor, the heterojunction is planar and the heterojunction area per unit area of a chip is small, whereby the current flowing through the two dimensional electron gas is limited. Therefore, the chip area must be increased in order to increase the power output of the FET. In addition, due to the scattering of electrons in the channel width direction, the performance of the FET cannot be increased.
Japanese Published Patent Application Hei. 4-17340 discloses a semiconductor device having a structure that solves these problems. That semiconductor device has a periodic concave-convex structure including stripe shaped convex portions and concave portions extending in the direction of the current flow at the heterojunction interface. This semiconductor device has increased heterojunction area per unit chip area. In addition, because many electrons are stored in the electron channel layer in the vicinity of the convex portion of the heterojunction relative to the other areas, a one dimensional carrier density distribution is formed along the stripe shape of the convex portion, whereby a pseudo one dimensional electron gas is formed, preventing scattering of electrons in the channel width direction and increasing the mobility of the electrons.
In a semiconductor device having such a structure, however, the quantity of electrons necessary for forming a pseudo one dimensional electron gas at the convex portion depends on the amplitude and period of the concave and convex portions of the heterojunction interface.